1. Field of the Invention
The present invention generally relates to semiconductor devices and more particularly to a semiconductor device that has a BGA (ball grid array) structure.
2. Description of the Related Art
With the demand for high speed, high performance and low cost, semiconductor devices are continuously increasing in integration density. In order to meet the intense demand for increased integration density in particular, various package structures have been proposed, including a QFP (quad flat package) structure as well as the BGA structure mentioned before, wherein a QFP device uses a flat resin package body having interconnection leads projecting laterally from a circumferential edge of the package body. In a BGA device, on the other hand, metal spheres or balls are provided on a bottom surface of a Dackage body as electrodes. By arranging the metal balls in rows and columns, it is possible to increase the number of the electrodes even when the size of the package body is small.
FIG.1 shows the construction of a typical QFP device 1, wherein the device 1 includes a package substrate 2 carrying thereon a plurality of semiconductor chips 3 on upper and lower major surfaces 2a and 2b. The package substrate 2 may be formed of a ceramic, and is encapsulated in a flat resin package body 5, wherein a number of interconnection leads 4 are provided at the peripheral edge of the package body 5. Each of the interconnection leads 4 is formed of an inner lead part 4a held within the resin package body 5 and an outer lead part 4b projecting outside the package body 5. The inner lead part 4a is connected to a conductor pattern 6 provided on the package substrate 2 by means of a bonding wire 7. The bonding wire 7 is also encapsulated in the resin package body 5. Further, the outer lead part 4b of the interconnection lead 4 is bent in the downward direction in the vicinity of the peripheral edge of the package body 5 to form a gull wing structure, wherein there is formed a part laterally bent at the distal end of the outer lead part 4b for contacting with a wiring pattern provided on a printed circuit board. Thus, the QFP device of FIG.1 is suitable for mounting using the art of SMT (surface mounting technology).
In the semiconductor device 1, it is possible to mount the semiconductor chips 3 on both the upper and lower major surfaces of the package substrate 2 as already noted. Thus, the device 1 is advantageous for increasing the density of mounting of the chips on a package substrate. On the other hand, such a construction of increased number of chips on a single chip substrate raises a problem in that the number of the leads 4 extending from the resin package body 5 increases significantly. With such an increase in the number of the leads 4, the pitch between the leads 4 has to be correspondingly reduced. Further, each lead has to have a reduced width. Thereby, the leads 4 become fragile and easily cause a short circuit when the device 1 is mounted upon a printed circuit board. In addition, high precision is required when mounting such a high density semiconductor device upon a printed circuit board.
FIG. 2 shows the construction of a conventional BGA device 11 that overcomes the foregoing problem of QFP device, wherein the illustrated device 11 has a plastic package body as will be described later.
Referring to FIG. 2, the BGA device 11 includes a printed circuit board 12 of a multiple layer structure, wherein the printed circuit board 12 has an upper major surface 12a on which a single semiconductor chip 13 is mounted by a die bonding process, and the like. Further, the printed circuit board 12 has a lower major surface 12b on which a plurality of solder bumps 14 are formed for external connection. Corresponding to each of the solder bumps 14, there is provided a through hole 16 in the printed circuit board 12, wherein the through holes 16 are connected to a wiring pattern (not shown) provided on the upper major surface 12a of the printed circuit board 12. Further, the printed circuit board 12, having a multiple layer construction as noted before, may include a plurality of such wiring patterns in a plurality of layers, each in electrical connection with a through hole 16. Thereby, the wiring pattern or patterns on the surface 12a of the printed circuit board 12 are connected to the semiconductor chip 13 by way of bonding wires 15. The semiconductor chip 13, the bonding wires 15 and the wiring patterns are encapsulated in a resin package body 17.
In the BGA device 11 of FIG. 2, an increase in the number of external connections is easily accomplished by increasing the number of the solder bumps 14 that may be provided on the entire bottom surface 12b of the printed circuit board 12, without reducing the pitch between the solder bumps 14. On the other hand, the BGA device 11 has a disadvantage in that the side of the printed circuit board 12 that can carry the semiconductor chip 13 is limited to the surface 12a. It has not been possible to provide the semiconductor chip 13 on both the upper and lower major surfaces 12a and 12b of the printed circuit board 12.